Gate-Level Static Approximate Adders: A Comparative Analysis
نویسندگان
چکیده
Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. realized using approximate adder, and many adder designs been put forward in the literature targeting acceptable trade-off between quality of results savings design metrics compared accurate adder. adders can classified into three categories as: (a) suitable FPGA implementation, (b) ASIC type (c) implementations. Among these, adders, are implementations particularly interesting given their versatility they typically designed at gate level. Depending on way approximation built two kinds as static dynamic adders. This paper compares analyzes both We consider evaluate performance a digital image processing application standard figures merit such peak signal noise ratio structural similarity index metric. provide corresponding For we considered Xilinx Artix-7 FPGA, 32/28 nm CMOS cell library. While inferences from this work could serve useful reference determine optimum application, particular, HOAANED, HERLOA M-HERLOA preferable.
منابع مشابه
Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis
Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4to 20-bits are considered for the less significant adder bit positions. The simulation results show that approx...
متن کاملComparative Performance Analysis of Various PPM Adders
This paper presents a comparative study of different redundant binary full adders (Plus-Plus-Minus (PPM) adder). These PPM adders are simulated to evaluate their performance in total power dissipation, speed and PDP. The performances of these circuits are based on 180nm process model at a supply voltage of 1.8V. We also proposed a new design for PPM adder using 13-transistors. The simulation re...
متن کاملA Comparative Approximate Economic Behavior Analysis Of Support Vector Machines And Neural Networks Models
متن کامل
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high Vth for good standby power and low Vth for h...
متن کاملNonlocal Automated Comparative Static Analysis
This paper reviews work on the^ development of a program Nasa for the automated comparative static analysis of parametrized nonlinear systems over parameter intervals. Nasa incorporates a fast and efficient algorithm Feed for the automatic evaluation of higher-order partial derivatives, as well as an adaptive homotopy continuation algorithm for obtaining all required iiutial conditions. Applica...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Electronics
سال: 2021
ISSN: ['2079-9292']
DOI: https://doi.org/10.3390/electronics10232917