Gate-Level Static Approximate Adders: A Comparative Analysis

نویسندگان

چکیده

Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. realized using approximate adder, and many adder designs been put forward in the literature targeting acceptable trade-off between quality of results savings design metrics compared accurate adder. adders can classified into three categories as: (a) suitable FPGA implementation, (b) ASIC type (c) implementations. Among these, adders, are implementations particularly interesting given their versatility they typically designed at gate level. Depending on way approximation built two kinds as static dynamic adders. This paper compares analyzes both We consider evaluate performance a digital image processing application standard figures merit such peak signal noise ratio structural similarity index metric. provide corresponding For we considered Xilinx Artix-7 FPGA, 32/28 nm CMOS cell library. While inferences from this work could serve useful reference determine optimum application, particular, HOAANED, HERLOA M-HERLOA preferable.

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ژورنال

عنوان ژورنال: Electronics

سال: 2021

ISSN: ['2079-9292']

DOI: https://doi.org/10.3390/electronics10232917